Mismatched output rise and fall times lead to asymmetric characteristics on the single-ended signals of a differential transmitter. This in turn results in a non-static common mode signal during bit transition events. This is illustrated in FIG. 1, where the solid traces 20 and 22 represent the single-ended components of the differential transmitter output with asymmetric rise and fall time, and the dashed trace 24 represents the impact of the asymmetric rise and fall time in the form of spikes on the common mode signal.
In certain transmitter applications it can be desirable to provide an edge-rate control feature. This can prove useful as a means to ensure that, under particularly fast process, voltage, and temperature operating conditions, output transition times can be slowed down to fall in the acceptable range called for by the applicable specification.
Edge rate control can also prove useful when a transmitter design targets a specific generation of a specification but also provides support for one or more legacy generations of the same specification (for example, targeting support for 12 Gb/s SAS but providing legacy support for prior generations operating at 6 Gb/s, 3 Gb/s or 1.5 Gb/s) which may have disparate and possibly incompatible maximum and minimum limits for output rise and fall times. In such cases, the edge rate control feature is typically activated when the transmitter is configured to support one of the legacy specification generations. Edge rate control may or may not be employed for the target specification generation, depending on its requirements.
Transition times for a transmitter are highly dependent on the effective resistance (load resistance) and capacitance (load capacitance) present at the transmitter output, which define RC time constants. FIG. 2A shows a diagram of transmitter 48 that has an input 50, an output 52, a driver 54 (which can also be referred to as an output driver), a capacitor 56, which has a load capacitance value CL, and a resistor 58, which has a load resistance value RL. FIG. 2B shows an inverter element 60, which is part of the driver 54. The resistive portion of the RC time constant of the transmitter 48 is dependent on the external load (RL), the capacitance (CL) at the transmitter output, parasitic elements, and the signal path inside the transmitter. The resistive paths of the transmitter are usually nominally designed to be the same during either a rising (RPU: pull-up resistance) or falling (RPD: pull-down resistance) transition. However, over silicon process variation, operating voltage and temperature, and random mismatch effects, RPU and RPD will vary in an absolute sense and with respect to each other. The rise time (trise) and fall time can be defined accordingly with dependency on RPU and RPD, as per Equation 1.
                              t          rise                ∝                  (                                                    R                PU                            ⁢                                                                R                  L                                )                            ⁢                              C                L                            ⁢                                                          ⁢                              t                fall                                      ∝                          (                                                R                  PD                                ⁢                                                                        R                    L                                    )                                ⁢                                  C                  L                                                                                        Equation        ⁢                                  ⁢        1            
FIG. 3A shows a voltage mode transmitter 62, elements of which are described in U.S. Pat. No. 7,501,851, granted Mar. 10, 2009. The voltage mode transmitter 62 has a driver structure that includes multiple unit cells 64, each with CMOS drivers 54 driving series resistances. The multiple unit cells 64 are connected in parallel and produce the outputs 66 and 68 as a function of the inputs 70 and 72, which are common to each unit cell 64. Each CMOS driver 54 includes an inverter element 60 shown at FIG. 3B. Each inverter element 60 has a PMOS device 74 and an NMOS device 76. For the voltage mode transmitter 62, the difference between RPU and RPD will be dictated by the matching of the on-resistance of the PMOS (rPMOS) and NMOS (rNMOS) devices 74 and 76 that make up the inverter element 60. For the drivers 54 illustrated in FIG. 3A, RPU and RPD can be expressed as per Equation 2, where the series resistance RSER 78 is a common resistor component, and rPMOS and rNMOS are distinct components for RPU and RPD, respectively.RPU=RSER+rPMOS RPD=RSER+rNMOS  Equation 2
Thus, an important source of rise and fall time mismatch in a voltage mode transmitter originates from mismatches in the on-resistance of the PMOS (rPMOS) and NMOS (rNMOS) devices 74 and 76 shown at FIG. 3B. RSER is a series resistance that can be attributable, for example, to a polysilicon resistor in some embodiments or to highly doped metals in other embodiments.
Also shown in FIG. 3A are a driver enable port 80 and a parallel termination enable port 82. The parallel transmission gate enable port 82 is connected to transmission gates 79. Such transmission gates 79 are sometimes used as a means to achieve amplitude control in a configurable voltage mode transmitter such as the voltage mode transmitter 62 of FIG. 3A. The transmission gates 79 do not form part of the pull-up or pull-down path resistances in the unit driver cells, but they do serve to establish the output impedance of the transmitter 62 when they are enabled. A unit drive cell would either be configured to operate in drive mode (DEN=1) or in parallel termination mode (PTEN=1). In parallel termination mode, the CMOS inverter-like drivers are disabled and the transmission gate is enabled. This establishes a shunt resistive path between the transmitter outputs TXOP and TXON, comprised of two RSER contributions and the effective resistance of the transmission gate. The transmission gate is built as a parallel connection of PMOS and NMOS devices.
A traditional form of edge rate control is achieved by blending between the normal data to be transmitted by the transmitter and a version of the data delayed by non-sequential circuit elements. A portion of the transmitter driver is configured to output the normal data, and another portion is configured to output the delayed data. Blending is achieved at the transmitter output node and controlled by adjusting the relative portion of the transmitter that outputs normal data to the portion that outputs delayed data.
Such a blending approach has advantages, for example, simplicity, but also has numerous disadvantages. This blending approach is good at slowing down output transition times when the amount of delay between the normal and delayed data paths is smaller than the transition times of the signals on the normal and delayed data paths. However, when the delay exceeds the transition times, then there is little or no effective blending anymore, resulting in “kinked” waveforms, as illustrated by the eye diagrams shown in FIG. 4, where a first waveform with an initial amount of time delay between the normal data path and a delayed data path is shown at reference numeral 50, and a second waveform with an increased amount of time delay between the normal data path and the delayed data path is shown at reference numeral 52.
The relative magnitude difference between the amount of combinational delay between the normal and delayed data through the transmitter and their transition times will vary as a function of process, voltage and temperature. This makes the effectiveness of the blending strategy fairly unpredictable and uncontrollable at design time.
A further complication of delayed-data/blending edge rate control is that the process of delaying the data through combinational circuit elements results in added jitter on the delayed data path. This in turn can increase jitter on the transmitted output as a function of how much delay is desired. When a transmitter design targets a specific generation of a specification, and also provides legacy generation support, the jitter penalty associated with using delayed-data path edge rate control for the most current generation may be prohibitive, in which case, edge rate control would be reserved exclusively for legacy generation support.
Therefore, improvements in the control of rise and fall times of transmitted signals are desirable.